1. Field of the Invention The present invention relates to a signal transmission technique. More particularly, a first aspect of the present invention relates to a driver circuit used for transmitting signals between LSI chips or between elements or circuit blocks in an LSI chip, and a second aspect of the present invention relates to a receiver circuit and signal transmission system capable of transmitting signals at high speed. Further, a third aspect of the present invention relates to a timing signal generator circuit of a wide range of operation frequencies, and a fourth aspect of the present invention relates to a signal transmission technique involving the driver circuit, receiver circuit, and signal transmission system, capable of transmitting signals at high speed.
2. Description of the Related Art
Recently, the performance of information processing equipment such as computers has improved greatly. In particular, an improvement in the performance of DRAMs (dynamic random access memories) and processors is drastic. To keep pace with such improvement, signal transmission speeds must be increased.
For example, a speed gap between a DRAM and a processor in a computer hinders the performance of the computer. As the size of each chip increases, not only signal transmission between chips but also signal transmission between elements or circuit blocks in each chip becomes critical to the performance of the chip. Also critical is signal transmission between devices that form a multiprocessor server or between a server and peripheral circuits. To realize high-speed signal transmission, it is required to provide a driver circuit capable of transmitting signals at high speed.
High-speed signal transmission is needed not only between discrete units such as between a server and a main storage device, between servers connected to each other through a network, and between printed boards but also between chips and between elements or circuit blocks in a chip due to an improvement in integration of LSIs and a decrease in power source voltage and signal amplitude. To improve the transmission speed, it is necessary to provide a receiver circuit and signal transmission system capable of correctly transmitting and receiving signals at high speed.
The receiver circuit must operate at a correct timing to receive signals transmitted at high speed between LSIs. To realize the correct reception timing, it is necessary to generate a correct timing signal. For this purpose, there are a DLL (delay locked loop) technique and a PLL (phase locked loop) technique. If a cable connecting a server to a main storage device is long or has poor transmission characteristics, an operation frequency must be dropped to correctly transmit signals through the cable. This requires a timing signal generator capable of generating a correct timing signal at high speed and operating in a wide frequency range. It also requires a signal transmission technique capable of preventing waveform disturbance due to high-frequency signal components and line-to-line interference.
Prior arts and the problems thereof will be explained later, and in detail, with reference to drawings.
An object of a first aspect of the present invention is to provide a driver circuit capable of correctly transmitting signals without waveform distortion or inter-code interference.
An object of a second aspect of the present invention is to provide a receiver circuit and a signal transmission system capable of correctly transmitting and receiving signals at high speed.
An object of a third aspect of the present invention is to provide a timing signal generator circuit having a simple structure capable of operating in a wide frequency range to generate a correct, high-speed timing signal without jitter.
An object of a fourth aspect of the present invention is to provide a signal transmission technique capable of correctly transmitting signals at high speed without waveform distortion due to high-frequency signal components or line-to-line interference.
According to a first aspect of the present invention, there is provided a driver circuit for transmitting signals, comprising an output driver; a front driver for driving the output driver; and a level adjuster for adjusting the output level of the front driver, so that the output driver outputs a signal having a specific level varied in response to an output level of the front driver.
The output driver may include a drain-grounded push-pull structure employing p-channel and n-channel MOS transistors. The output driver may be a voltage amplifier circuit whose output level is varied by adjusting an output voltage level of the front driver. The output driver may be a current-voltage converter circuit whose output voltage level is varied by adjusting an output current level of the front driver. The output driver may include a feedback circuit for dropping output impedance.
The front driver may include a variable gain unit cooperating with the level adjuster, to adjust a level of an input signal level; and an amplifier for amplifying the level-adjusted input signal. The front driver may be a current limiting inverter for receiving an input signal, an output level of the current limiting inverter being adjusted by controlling a current passing thereto by the level adjuster. An output of the output driver may be changed in response to a sequence of past digital values, to equalize characteristics of a transmission line.
The front driver may comprise a plurality of drivers that are commonly connected to the output driver, the drivers of the front driver receiving data generated from a sequence of past digital data provided by the output driver and equalizing characteristics of a transmission line. The drivers of the front driver may have respective coefficients, multiply received data by the coefficients, and supply the products to the output driver.
The front driver may comprise first and second drivers, a digital input signal to the driver circuit being directly supplied to the first driver of the front driver, and at the same time, being delayed by a bit time, inverted, and supplied to the second driver of the front driver, thereby equalizing characteristics of a transmission line. The first and second drivers of the front driver may be arranged in parallel with each other; the second driver of the front driver may multiply the delayed and inverted signal by a coefficient; and the outputs of the first and second drivers of the front driver may be added to each other to drive the output driver. The characteristics of the transmission line may be equalized by compensating for attenuation in high-frequency components in signals that are provided by the output driver and are transmitted through the transmission line. The front driver may comprise a plurality of driver pairs, the driver pairs of the front driver being interleaved to carry out parallel-to-serial conversion.
The output driver may include a source-grounded push-pull structure employing p-channel and n-channel MOS transistors. A gate voltage of the p-channel MOS transistor of the output driver may be set above an intermediate voltage, which is between a high source voltage and a low source voltage, and a gate voltage of the n-channel MOS transistor of the output driver may be set below the intermediate voltage when the output driver provides the intermediate voltage. The gate of the n-channel MOS transistor may be driven by a drain-grounded n-channel MOS circuit and the gate of the p-channel MOS transistor may be driven by a drain-grounded p-channel MOS circuit.
The output driver may be driven by a voltage that is lower than the high source voltage by a predetermined value and a voltage that is higher than the low source voltage by a predetermined value. The output driver may include a replica driver that equalizes an intermediate voltage between voltages for driving the output driver to an intermediate voltage between the high source voltage and the low source voltage.
According to a second aspect of the present invention, there is provided a receiver circuit comprising a capacitor network for receiving differential input signals, having a capacitor for accumulating charge and a switch for switching the supply of the differential input signals to the a capacitor; and a comparator having inverters for amplifying the outputs of the capacitor network and a common-mode feedback circuit for receiving the outputs of the inverters and maintaining a common-mode voltage substantially at a fixed value.
Further, according to a second aspect of the present invention, there is also provided a signal transmission system having a differential driver circuit; a cable connected to the differential driver circuit, for transmitting differential signals provided by the differential driver circuit; and a receiver circuit connected to the cable, for detecting the differential signals, wherein the receiver circuit comprises a capacitor network for receiving differential input signals, having a capacitor for accumulating charge and a switch for switching the supply of the differential input signals to the capacitor; and a comparator having inverters for amplifying the outputs of the capacitor network and a common-mode feedback circuit for receiving the outputs of the inverters and maintaining a common-mode voltage substantially at a fixed value.
The capacitor network may reduce a common-mode voltage in a low-frequency region of the differential input signals, and the comparator may reduce a common-mode voltage in a high-frequency region of the differential input signals. The capacitor network may form a partial response detector circuit. The receiver circuit may further comprise a precharge circuit arranged at input terminals of the comparator. The precharge circuit may precharge the comparator by applying a predetermined source voltage to the input terminals of the comparator. The precharge circuit may precharge the comparator by feeding the outputs of the inverters installed at the input terminals of the comparator back to the input terminals of the comparator.
The inverters installed in the comparator may be each a constant-current-load inverter. The inverters installed in the comparator may be each a complementary MOS inverter. The common-mode feedback circuit may include a detector having a differential amplifier having two pairs of input transistors; and a current-mirror-connected feedback circuit. The common-mode feedback circuit may include a detector for detecting a common mode voltage by combining the outputs of two complementary MOS inverters that amplify a pair of signal lines. Each amplifying stage of the comparator may be a complementary MOS inverter.
The comparator may include clamp circuits for suppressing an amplitude of each output signal of the comparator below a predetermined range of levels. The predetermined range of levels may be a range of source voltages. The comparator may include a control circuit for changing, under a differential mode of the common-mode feedback circuit, an amplification degree for amplifying signals provided by the capacitor network, the amplification degree being increased under the differential mode after amplifying the signals provided by the capacitor network so that the common-mode feedback circuit may operate as a latch circuit.
According to a third aspect of the present invention, there is provided a timing signal generator circuit comprising a first timing signal generator for receiving a clock signal, giving the clock signal a variable effective delay, and generating a first timing signal; a phase controller for controlling a phase of the first timing signal; and a second timing signal generator for dividing a frequency of the first timing signal by an integer and generating a second timing signal whose frequency is a quotient of the frequency of the first timing signal divided by the integer.
The phase controller may move forward or back the phase of the first timing signal step by step so that the phase of the first timing signal may change in a range of substantially 360 degrees with respect to the clock signal serving as a reference. The second timing signal generator may be a frequency dividing circuit. The frequency dividing circuit may employ a variable frequency dividing ratio. An operation frequency of the first timing signal generator and the frequency dividing ratio of the frequency dividing circuit may be changed so that the first timing signal may have an optional frequency that is lower than a maximum clock frequency of the first timing signal generator. The first timing signal generator may be a variable delay circuit; the second timing signal generator may be a delay generator circuit for generating an effective delay by counting the clock signal; and the output of the delay generator circuit may be supplied to the variable delay circuit.
The first timing signal generator may be a variable delay circuit; and the second timing signal generator may be a circuit for gating the first timing signal in response to an output of a sequential circuit that receives the clock signal or the first timing signal. The variable delay circuit may include a multiphase clock generator circuit that receives the clock signal; and a phase interpolator that receives output signals of the multiphase clock generator circuit.
The first timing signal generator may include a tapped delay stage; and a selector for selecting one of the output signals of the tapped delay stage. The timing signal generator circuit may further comprise a phase locked loop circuit that multiplies the clock signal by an integer and providing the first timing signal generator with a product signal whose frequency is higher than the frequency of the clock signal that is used for signal transmission. The phase controller may include a phase comparison circuit for comparing the phase of the second timing signal with the phase of an external clock signal and providing an output signal to control the phase of the first timing signal.
According to a fourth aspect of the present invention, there is provided a method of transmitting a signal from a driver to a receiver, comprising the step of making a sum of a rise time and a fall time of each code contained in the signal transmitted from the driver equal to or longer than a bit time.
The method may further comprise the step of determining a value in a bit time in a signal received at the receiver according to a latter half of the bit time where the received signal reaches a peak. The method may further comprise the steps of transmitting, from the driver, a sequence of reference codes alternating between 0 and 1; detecting, at the receiver, the reference codes and determining reception timing used as a threshold to detect 0s and 1s in a received signal; and shifting, at the receiver, a phase of the determined reception timing by a predetermined value, to provide optimum reception timing. The method may further comprise the step of carrying out, at the receiver, an equalizing process to remove inter-code interference from a received signal. The removal of inter-code interference may include the steps of adjusting, at the driver, a rise time of a signal to be transmitted from the driver; and carrying out, at the receiver, the equalizing process.
Further, according to a fourth aspect of the present invention, there is provided a signal transmission system for transmitting a signal from a driver circuit to a receiver circuit through a transmission line, comprising a code length controller provided for the driver circuit, for making a sum of a rise time and a fall time of each code contained in a signal to be transmitted from the driver equal to or longer than a bit time.
The signal transmission system may further comprise a reception signal determination circuit, provided for the receiver circuit, for determining a value in a bit time in a signal received at the receiver according to a latter half of the bit time where the signal reaches a peak. The code length controller may include a multiphase clock generator for generating multiphase clock signals that are synchronized with a transmission clock signal; and a plurality of unit drivers sequentially driven in response to multiphase clock signals.
The code length controller may include a plurality of constant-current output drivers driven by a first binary signal to be transmitted and a second binary signal formed by delaying the first binary signal by a bit time or an integer multiple of the bit time; a current sum generator for combining outputs of the constant-current drivers to provide a current sum of the constant-current drivers; and an integration circuit for integrating the current sum to provide a voltage. The reception signal determination circuit may include a reception timing detector for receiving a sequence of reference codes alternating between 0 and 1 from the driver circuit, detecting the reference codes, and determining reception timing used as a threshold to detect 0s and 1s in a received signal; and an optimum reception timing generator for shifting the phase of the determined reception timing by a predetermined value to provide optimum reception timing.
The receiver circuit may include an equalizing circuit for removing inter-code interference from a received signal. The driver circuit may include an adjuster for adjusting a rise time of a signal to be en transmitted from the driver circuit as well as adjusting an equalizing process to be carried out by the receiver circuit, so that inter-code interference may be removed at the receiver side.
Further, according to a fourth aspect of the present invention, there is also provided a driver circuit for transmitting a signal, comprising a code length controller for making a sum of a rise time and a fall time of each code contained in a signal to be transmitted equal to or longer than a bit time.
The code length controller may include a multiphase clock generator for generating multiphase clock signals that are synchronized with a transmission clock signal; and a plurality of unit drivers sequentially driven in response to the multiphase clock signals. The code length controller may include a plurality of constant-current output drivers driven by a first binary signal to be transmitted and a second binary signal formed by delaying the first binary signal by a bit time or an integer multiple of the bit time; a current sum generator for combining outputs of the constant-current drivers to provide a current sum of the constant-current drivers; and an integration circuit for integrating the current sum to provide a voltage.
In addition, according to a fourth aspect of the present invention, there is also provided a receiver circuit for receiving a signal in which a sum of a rise time and a fall time of each code is equal to or longer than a bit time, comprising a reception signal determination circuit for determining a value in a bit time in a signal received at the receiver according to a latter half of the bit time where the received signal reaches a peak.
The reception signal determination circuit may include a reception timing detector for receiving a sequence of reference codes alternating between 0 and 1, detecting the reference codes, and determining reception timing used as a threshold to detect 0s and 1s in a received signal; and an optimum reception timing generator for shifting a phase of the determined reception timing by a predetermined value to provide optimum reception timing. The receiver circuit may include an equalizing circuit for removing inter-code interference from a received signal.